This invention generally relates to semiconductor processing methods including photolithographic patterning and more particularly to a method for replicating alignment marks and preserving the optical signal integrity of alignment marks following an oxide CMP process.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. With the high integration of the semiconductor devices, the accuracy of formation of feature patterns overlying a previously defined semiconductor device level is increasingly difficult as critical dimensions shrink. Overlay accuracy, also referred to as registration is critical to proper functioning of a semiconductor device. To successfully pattern an overlying feature level on the wafer, the wafer feature pattern must be accurately aligned with a newly applied pattern image included in a reticle for proper transfer of the image to the photoresist layer on the wafer.
In forming the various levels of a multi-level semiconductor device including shallow trench isolation features, semiconductor wafer alignment for positioning the semiconductor wafer for subsequent device feature patterning is critical. In a typical photolithographic patterning procedure, an automated stepper, for example, an ASM Lithography photo system sequentially positions the wafer beneath a photoimaging system for transferring a patterned photoimage of device features formed a reticle to expose a photoresist material overlying the semiconductor wafer surface. As positioning of the process wafer is critical for forming semiconductor features, methods for forming and preserving alignment marks to provide the necessary optical contrast have evolved to reduce optical alignment errors during the optical signal sensing and alignment process during photolithography.
Several wafer alignment strategies exist for using different patterns and locations to achieve the alignment of a semiconductor wafer to a reticle containing an image to be transferred to the wafer. These strategies vary from alignment marks located between shot sites (also known as chip sites) to global alignment marks located in two shot sites at the periphery of the wafer. There are also global strategies in which the alignment marks are located between shot sites in the more peripheral regions of the wafer. The overlay accuracy required for proper alignment, frequently referred to as an overlay budget is about one-third of the critical dimension. As device technologies scale to about 0.10 microns and below, conventional method for forming and replicating alignment marks are no longer sufficiently accurate.
In one approach for global alignment, at least two areas at the wafer periphery are selected, typically located on opposite sides of the wafer diameter and include a series of parallel trenches covering a rectangular or square area of about 50 square microns to about 400 square microns referred to as zero-level alignment marks that are etched into the silicon wafer before other processing steps. The global alignment marks are subsequently replicated in each subsequent level of manufacturing a multi-level semiconductor device.
Shallow trench isolation (STI) is a preferred electrical isolation technique especially for a semiconductor chip with high integration. STI features can be made using a variety of methods including, for example, the Buried Oxide (BOX) isolation method for shallow trenches. The BOX method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO2), also referred to as an STI oxide which is then chemically mechanically polished (CMP) to remove the overlying layer of STI oxide to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the substrate, for example, silicon, and are typically between 0.3 and 1.0 microns deep.
Broadly speaking, conventional methods of producing a shallow trench isolation feature include forming a hard mask, for example silicon nitride, over a semiconductor substrate followed by photolithographically patterning and anisotropically etching STI trench features into the semiconductor substrate. Subsequently, the STI trenches are backfilled with SiO2 also referred to as an STI oxide by a CVD process followed by a chemical mechanical polish (CMP) process to polish back the STI oxide to define oxide filled STI trenches. Alignment mark areas on the wafer process surface undergo parallel processing including deposition of an STI oxide layer and are replicated for subsequent wafer alignment according to prior art processes by clearing out the STI oxide over the alignment mark areas prior to CMP. For example, the relative contrast of the alignment marks which are detected by an auto-imaging system using for example, a Helium-Neon laser having a wavelength between about 500 nm to about 630 nm is generally unaffected by dielectric films transparent in this wavelength range which present little interference with reflections from an underlying alignment mark area, typically having a higher extinction coefficient material to provide contrast producing reflections. During the processing of several levels in a multi-level semiconductor device, the alignment mark areas frequently are covered with high extinction coefficient materials such as SiGe, silicon carbide (e.g., SiC), silicon oxynitride (e.g. SiON), metal salicides, polysilicon, and metallic layers. While the alignment mark trenches are frequently not completely covered thereby losing their definition, the sharpness of the definition is decreased. As overlay budgets approach 20 to 30 nanometers for 0.10 micron critical dimensions and lower, a small decrease in the definition of the alignment marks by overlayers of high extinction coefficient materials is increasingly detrimental to overlay accuracy. In many cases an additional step to photolithographically pattern and etch the alignment mark area is economically prohibitive in terms of process cycle time and material cost.
For example referring to FIG. 1A are shown STI trenches e.g., 12A, 12B, and 12C formed through the thickness of a hard mask layer 14, for example silicon nitride (e.g., Si3N4), and underlying pad oxide layer (not shown), and into a silicon substrate 10. Adjacent the STI trenches is shown a portion of an alignment mark area including alignment mark trenches e.g., 16A and a portion of alignment mark trench 16B, the trenches formed by etching the silicon substrate 10 prior to other processing steps including forming the overlying silicon nitride layer 14. It will be appreciated that although the structures are depicted as adjacent one another, that the STI trenches and alignment mark trenches are typically separated on the wafer process surface as indicated by lines e.g., 13.
Referring to FIG. 1B, an STI oxide layer 18 is deposited over the process surface followed by a photolithographic patterning process to form a protective photoresist layer e.g., 20 to cover active areas including STI trench areas overlying the STI trenches e.g., 12A, 12B, and 12C and exposing areas of the STI oxide layer on the process surface including the wafer alignment mark areas. For example, frequently a reverse mask etch process is carried out to remove a portion of the STI oxide layer 18 overlying relatively featureless areas of the process surface to improve a subsequent CMP polishing uniformity. Referring to FIG. 1C, the STI oxide overlying the alignment mark areas including trenches 16A and 16B is frequently removed in the reverse mask etch process while leaving the STI oxide layer 18 and protective photoresist layer e.g. 20 overlying the STI trench area.
Referring to FIG. 1D, after removing the protective photoresist layer e.g., 20, an oxide CMP process is then carried out to remove the STI oxide layer 18 overlying the STI trench areas. During the oxide CMP process, however, the silicon nitride layer 14 is either thinned or completely polished through in areas around the alignment trenches, for example at corner portions, e.g., 16C of the alignment trenches, undesirably degrading the optical contrast of the alignment marks. Further, a subsequent hot phosphoric acid etching process to remove the silicon nitride layer 14 may result in undesired etching of an underlying material, for example a silicon substrate or other etching susceptible layer, for example if an underlying pad oxide layer overlying a silicon substrate is partially removed in the CMP process. For example, designs of various memory and logic devices, for example flash memory, incorporate an etching susceptible layer underlying a relatively thinner silicon nitride to maintain an STI trench aspect ratio. To prevent the STI oxide CMP process from polishing through or unacceptably thinning the corner portions of the alignment trenches, hard mask layers such as silicon nitride are required to be thick enough to survive the STI oxide CMP process. For example, the thicker the oxide layer and the longer the oxide polishing process required, the greater the potential of preferential polishing over the alignment mark area requiring a thicker hard mask layer. As a result, methods of the prior art for preserving and replicating alignment marks limits the design thickness of layers, for example both hard mask layers and oxide layers in the design of various logic and memory devices in order to prevent degrading the alignment mark area optical contrast during and following a CMP process.
Therefore, there is a need in the semiconductor processing art to develop an improved method for replicating alignment marks to preserve optical contrast integrity thereby improving overlay accuracy in semiconductor wafer photolithography and allowing a greater degree of freedom in design of film stacks in a semiconductor device design process.
It is therefore an object of the invention to an improved method for replicating alignment marks to preserve optical contrast integrity thereby improving overlay accuracy in semiconductor wafer photolithography and allowing a greater degree of freedom in design of film stacks in a semiconductor device design process including overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for protecting an alignment mark area during a CMP process.
In a first embodiment, the method includes forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.